Security

User Password

Exit

Save Changes and Exit

Discard Changes and Exit

Save Changes and Reset

Discard Changes and Reset

Save Changes

Discard Changes

Back quote

`

Tilde

~

Exclamation point

!

At sign

@

Pound sign

#

Dollar sign

$

Percent sign

%

Caret

^

Ampersand sign

&

Asterisk

*

Left parenthesis

(

Right parenthesis

)

Underscore

_

Plus sign

+

Minus sign

-

Equal sign

=

Left bracket

[

Right bracket

]

Back slash

\

Left brace

{

Right brace

}

Vertical bar

|

Semi-colon

;

Apostrophe

'

Colon

:

Quotation marks

"

Comma

,

Dot

.

Forward slash

/

Left angle bracket

< 

Right angle bracket

> 

Question mark

?

BIOS Information

Project Name

Displays the project name.

N/A

Product Name

Displays the product name.

N/A

BIOS Version

Displays the BIOS version.

N/A

Build Date and Time

Displays the compiling date and time of the BIOS build.

N/A

System Uuid

Displays the universally unique identifier (UUID) of the system.

N/A

Access Level

Displays the privileges of the current login role.

N/A

Platform Information

Processor

Displays the CPU ID and stepping.

N/A

PCH

Displays the platform controller hub (PCH) model.

N/A

RC Revision

Displays the RC version.

N/A

Memory Information

Total Memory

Displays the total memory capacity of DRAM in GB.

N/A

Usable Memory

Displays the usable DRAM memory capacity, in GB.

When a specific memory mode, such as memory mirroring, is set, the total memory capacity is different from the actual usable memory capacity. This item displays the actual usable memory capacity.

N/A

Total DCPMM Memory

Displays the total memory capacity of DCPMM in GB.

DCPMM should be used together with DRAM. For information about how to install DCPMM, see the user guide.

N/A

Current Memory Frequency

Displays the current memory frequency.

For information about setting the memory frequency, see "Memory Configuration submenu."

N/A

System Language

Displays the language used in the system.

The BIOS supports English and simplified Chinese.

To switch between the languages, press Enter.

English

Setup Mode

Set the BIOS setup mode.

Options:

·     Text.

·     Graphic.

Graphic

System Date

Displays the system date. You can change the system date as needed.

The system date is in the format of mm/dd/yyyy. To move between the month, day, and year fields, press Enter or Tab. To change the value for the selected field, use the following method:

·     Press + to increase the value by 1.

·     Press - to decrease the value by 1.

N/A

System Time

Displays the system time. You can change the system time as needed.

The system time is in the format of hh:mm:ss in 24-hour format. To move between the hour, minute, and second fields, press Enter or Tab. To change the value for the selected field, use the following method:

·     Press + to increase the value by 1.

·     Press - to decrease the value by 1.

N/A

Socket Configuration

Submenu for configuring the socket.

Platform Configuration

Submenu for configuring the platform.

Trusted Computing

Submenu for configuring trusted computing.

ACPI Settings

Submenu for configuring advanced configuration and power interface (ACPI) settings.

Serial Port Console Redirection

Submenu for configuring serial port console redirection.

PCI Subsystem Settings

Submenu for configuring the PCI subsystem.

USB Configuration

Submenu for configuring USB.

CSM Configuration

Submenu for configuring the compatibility support module (CSM).

NVMe Configuration

Submenu for configuring NVMe.

Network Configuration

Submenu for configuring network stacks.

Miscellaneous Configuration

Other configuration.

iSCSI Configuration

Submenu for configuring iSCSI.

This submenu is available only for the B5700, R5300, and R5500 G5.

Intel(R) VROC sSATA Controller

Submenu for configuring Intel(R) VROC sSATA controller.

This submenu is available only when the sSATA mode is set to RAID in the PCH settings.

Intel(R) VROC SATA Controller

Submenu for configuring Intel(R) VROC SATA controller.

This submenu is available only when the SATA mode is set to RAID in the PCH settings.

Intel(R) Virtual RAID on CPU

Submenu for configuring Intel(R) Virtual RAID on CPU (Intel VROC).

This submenu is available only when VMD is enabled.

Driver Health

Submenu for viewing the health state of drivers or controllers.

This submenu is available only in UEFI boot mode.

Processor Configuration

Submenu for configuring processors, as shown in Figure 49, Figure 50, and Figure 51.

The submenu items are described in Table 9.

Common RefCode Configuration

Submenu for configuring the common reference code, as shown in Figure 56.

The submenu items are described in Table 12.

Uncore Configuration

Submenu for configuring Uncore parameters, as shown in Figure 57.

The submenu items are described in Table 13.

Memory Configuration

Submenu for configuring memory parameters, as shown in Figure 60 and Figure 61.

The submenu items are described in Table 16.

IIO Configuration

Submenu for configuring Integrated I/O module (IIO) parameters, as shown in Figure 69.

The submenu items are described in Table 22.

Advanced Power Management Configuration

Submenu for configuring advanced power management parameters, as shown in Figure 77.

The submenu items are described in Table 29.

Per-Socket Configuration

Access the submenu for per-socket configuration, as shown in Figure 54.

The submenu items are described in Table 10.

N/A

Processor BSP Revision

Displays the processor revision.

N/A

Processor Socket

Displays the sequence number of the processor socket.

N/A

Processor ID

Displays the processor ID.

N/A

Processor Frequency

Displays the processor frequency.

N/A

Processor Max Frequency

Displays the maximum frequency allowed for each processor.

N/A

Processor Min Frequency

Displays the minimum frequency allowed for each processor.

N/A

Processor TDP

Displays the thermal design power (TDP) of the processor.

N/A

Microcode Revision

Displays the microcode revision.

N/A

L1 Cache RAM (Per Core)

Displays the capacity of the level-1 processor cache.

N/A

L2 Cache RAM  (Per Core)

Displays the capacity of the level-2 processor cache.

N/A

L3 Cache RAM  (Per Package)

Displays the capacity of the level-3 processor cache.

N/A

Processor X Version

Displays the version of CPU X. This field displays not present if the CPU is absent.

Hyper-Threading [ALL]

This item is unavailable if the processer does not support hyper-threading.

Select Enabled or Disabled to enable or disable hyper-threading for the processors.

Hyper-threading allows a single processor to handle thread-level parallelism by enabling each physical processor core to function as two logical processor cores. This improves processor operating efficiency by enabling the processors to be compatible with multi-threaded OSs and software and reducing processor idle time.

Enabled

Check CPU BIST Result

Select Enabled or Disabled to enable or disable CPU built-in-self test (BIST).

Enabled

Hardware Prefetcher

Select Enabled or Disabled to enable or disable hardware prefetcher.

If hardware prefetcher is enabled, the processor prefetches instructions or data from memory to L2 cache before processing the instructions or data. This feature helps improve system performance by reducing memory access time and eliminating potential bottlenecks.

Enabled

L2 RFO Prefetch Disable

Select Enabled or Disabled to enable or disable L2 read for ownership (RFO) prefetch.

RFO is the process of reading cache rows from memory into the cache before they are written to memory.

Disabled

Adjacent Cache Prefetch

Select Enabled or Disabled to enable or disable adjacent cache prefetcher.

Adjacent cache prefetcher is also referred to as mid-level cache (MLC) prefetcher. This feature provides system optimization for applications that require high-frequency SAM. You can disable this feature when a large amount of RAM is needed.

Enabled

DCU Streamer Prefetcher

Select Enabled or Disabled to enable or disable data cache unit (DCU) stream prefetcher.

If the DCU stream prefetcher is enabled, the processor improves data processing and system performance by prefetching the stream and sending it to the L1 cache.

Enabled

DCU IP Prefetcher

Select Enabled or Disabled to enable or disable DCU IP prefetcher.

If the DCU IP prefetcher is enabled, the processor prefetches IP addresses to improve network connectivity and system performance.

Enabled

LLC Prefetch

Select Enabled or Disabled to enable or disable the L3 or last level cache (LLC) prefetcher.

·     R6900 G5: Disabled

·     Other servers: Enabled

Extended APIC

Select Enabled or Disabled to enable or disable the extended APIC mode. If the total number of processor cores exceeds 256, enable this mode as a best practice for the operating system to better support the processor multi-core feature.

Disabled

Enable Intel(R) TXT

Select Enabled or Disabled to enable or disable the support for the Intel trusted execution technology (TXT).

Intel TXT provides comprehensive data security protection in a virtualized computing environment.

NOTE:

To avoid potential security problems, set the debug mode to Disabled before enabling Intel TXT.

Before enabling this feature, make sure you have finished the prerequisites described in Configuring TXT (for the R4700/R4900/R6900 G5 server only).

Disabled

VMX

This item is configurable only when Enable Intel(R) TXT is set to Disabled.

Select Enabled or Disabled to enable or disable Intel virtual machine extensions (VMX).

VMX improves server hardware resource usage by allowing the virtualization layer or OS that supports VMX to use Intel hardware virtualization capabilities.

For virtualization layers or OSs that do not support VMX, this feature does not take effect even if it is enabled.

Enabled

Enable SMX

This item is unconfigurable when Enable Intel(R) TXT is set to Enabled.

Select Enabled or Disabled to enable or disable the safer mode extensions (SMX).

Disabled

PKG CST CONFIG CONTROL MSR Lock

Select Enabled or Disabled to enable or disable package C-state configuration control MSR lock.

Enabled

AES-NI

Select Enabled or Disabled to enable or disable the support for Intel Advanced Encryption Standard New Instructions (AES-NI).

AES-NI can promote the encryption and decryption speed for applications.

Enabled

Total Memory Encryption (TME)

Select Enabled or Disabled to enable or disable total memory encryption.

This feature ensures that all memory accessed by processors are encrypted, protecting the system memory from hardware physical attacks.

Disabled

Total Memory Encryption Multi-Tenant (TME-MT)

This item is configurable only when Total Memory Encryption (TME) is set to Enabled.

Select Enabled or Disabled to enable or disable multi-tenant total memory encryption.

Disabled

Max TME-MT Keys

This item is available only when Total Memory Encryption (TME) is set to Enabled.

Displays the maximum number of TME-MT keys.

N/A

SGX Factory Reset

This item is configurable only when Total Memory Encryption (TME) is set to Enabled.

Select Enabled or Disabled to enable or disable SGX factory reset.

Disabled

SW Guard Extensions(SGX)

Select Enabled or Disabled to enable or disable SW Guard Extensions (SGX). This feature provides hardware-based memory encryption that can isolate specific application program codes and data in memory.

This item is configuration only when the following requirements are met:

·     DDR4 memory: All white memory slots are populated with DIMMs.

·     UMA-Based Clustering is set to Disable (All2All).

·     Numa is set to Enabled.

·     ADDDC Sparing is set to Disabled.

Disabled

SGX Package Info In-Band Access

This item is configurable only when Total Memory Encryption (TME) is set to Enabled.

Select Enabled or Disabled to enable or disable SGX package info in-band access.

Disabled

PRMRR Size

This item is configurable only when SW Guard Extensions(SGX) is set to Enabled.

Set the size of the Processor Reserved Memory Range Register. Options include:

·     2G.

·     4G.

·     8G.

·     16G.

2G

SGX QoS

This item is configurable only when Total Memory Encryption (TME) is set to Enabled.

Select Enabled or Disabled to enable or disable SGX QoS.

Disabled

Select Owner EPOCH input type

This item is configurable only when SW Guard Extensions (SGX) is set to Enabled.

Select the owner EPOCH input type. Options include:

·     Manual User Defined Owner EPOCHs.

·     Change to New Random Owner EPOCHs.

Manual User Defined Owner EPOCHs

Software Guard Extensions Epoch 0

Set the software guard extensions EPOCH value for SGX field 0. The value must be a hexadecimal number.

If Select Owner EPOCH input type is set to Change to New Random Owner EPOCHs, this field displays a random value.

N/A

Software Guard Extensions Epoch 1

Set the software guard extensions EPOCH value for SGX field 1. The value must be a hexadecimal number.

If Select Owner EPOCH input type is set to Change to New Random Owner EPOCHs, this field displays a random value.

N/A

SGXLEPUBKEYHASHx Write Enable

This item is configurable only when SW Guard Extensions(SGX) is set to Enabled.

Select Enabled or Disabled to enable or disable SGXLEPUBKEYHASHx write.

Disabled

SGXLEPUBKEYHASH0

This item is configurable only when SGXLEPUBKEYHASHx Write Enable is set to Enabled.

Set the 0^th to 7^th bytes for SGX to start SGX Launch Enclave Public Key Hash.

0

SGXLEPUBKEYHASH1

This item is configurable only when SGXLEPUBKEYHASHx Write Enable is set to Enabled.

Set the 8^th to 15^th bytes for SGX to start SGX Launch Enclave Public Key Hash.

0

SGXLEPUBKEYHASH2

This item is configurable only when SGXLEPUBKEYHASHx Write Enable is set to Enabled.

Set the 16^th to 23^rd bytes for SGX to start SGX Launch Enclave Public Key Hash.

0

SGXLEPUBKEYHASH3

This item is configurable only when SGXLEPUBKEYHASHx Write Enable is set to Enabled.

Set the 24^th to 31^st bytes for SGX to start SGX Launch Enclave Public Key Hash.

0

Enable/Disable SGX Auto MP Registration Agent

This item is configurable only when SW Guard Extensions(SGX) is set to Enabled.

Select Enabled or Disabled to enable or disable SGX auto MP registration agent for registration with the platform.

Enabled

CPU Socket N Configuration

Submenu for configuring processor N, as shown in Figure 55. N represents the processor number. The screen displays only present processors.

The submenu items are described in Table 11.

Available Core Bitmap / Number

Displays the available core bitmap and core quantity.

N/A

Active Core Bitmap / Number

Displays the active core bitmap and core quantity.

Available core quantity = Active core quantity + Disabled core quantity

N/A

Core Disable Number

Select the number of the cores to be disabled. The configuration takes effect after the server starts.

To enable all cores of the processor, set the value to 0.

You can set the Core Disable Number to a number equal to or less than the available core quantity.

For example, if 18 cores are available and 4 cores are disabled, only 14 cores are active.

NOTE:

Generally, the more cores you enable, the better the computing performance. Please be cautious when you disable cores.

0

MMCFG Base

This item is not supported by the R6900 G5. Non-professionals are not recommended to modify this configuration, which may cause a shortage of MMIO resources, resulting in the failure of BIOS to start up.

Set the MMCFG base.

Options include:

·     1G.

·     1.5G.

·     1.75G.

·     2G.

·     2.25G.

·     3G.

·     Auto.

Auto.

MMIO High Base

This item is not supported by the R6900 G5.

Set the MMIO high base address for PCIe modules over 4G.

Options include:

·     56T.

·     40T.

·     32T.

·     24T.

·     16T.

·     12T.

·     4T.

·     2T.

·     1T.

·     512G.

 CAUTION:

The upper limit of the MMIO high base address is 64T. If the sum size of MMIO high base and size allocated to each stack exceeds 64T, the system hangs at startup. For the B5700, R4300, R4700, R4900, R5300, and R5500 G5, make sure that the sum of MMIO high base and MMIO high granularity size multiplied by 10 is less than 64T.

·     For the R5300 and R5500 G5: 32T.

·     For the other servers: 56T.

MMIO High Granularity Size

This item is not supported by the R6900 G5.

Set the MMIO high granularity size. By default, the MMIO size allocated to each stack is equal to the specified size. Make sure the value is adjusted based on the requirements of installed PCIe devices on MMIO high base address over 4G and do not change it arbitrarily. If a large number of PCIe devices, especially GPUs, are installed, you can increase the MMIO high granularity size to increase the MMIO high base space, so as to ensure the correct allocation of MMIO high base resources to PCIe devices.

Options include:

·     1G.

·     4G.

·     16G.

·     64G.

·     256G.

·     1024G.

·     4096G.

 CAUTION:

The upper limit of the MMIO high base address is 64T. If the sum size of MMIO high base and size allocated to each stack exceeds 64T, the system hangs at startup. For the B5700, R4300, R4700, R4900, R5300, and R5500 G5, make sure that the sum of MMIO high base and MMIO high granularity size multiplied by 10 is less than 64T.

·     For the R5300 and R5500 G5: 4096G.

·     For the other servers: 64G.

Isoc Mode

Select whether to enable the Isoc mode.

Options:

·     Enabled.

·     Disabled.

·     Auto.

Auto

Numa

Select Enabled or Disabled to enable or disable non-uniform memory access (NUMA).

Under NUMA, a processor can access its own local memory faster than non-local memory.

Enabled

UMA-Based Clustering

Select the UMA-based clustering (UBC) mode. Options include:

·     Hemisphere (2-clusters)—Enable the UBC mode (also known as Hemisphere (HEMI). This mode allows affinity to exist between memory address and LLC slices to minimize distance memory address and cached LLC. This mode is available only when memory modules are populated in a symmetrical way and SNC is disabled.

·     Disable (All2All)—Disable the UBC mode.

Hemisphere (2-clusters)

Uncore General Configuration

Submenu for configuring the Uncore General Settings.

Uncore Status

Displays the Uncore status.

N/A

Link Frequency Select

Select the UPI link frequency.

Options:

·     9.6GT/s.

·     10.4GT/s.

·     11.2GT/s.

·     Auto.

Auto

KTI Prefetch

This item is available only for the R6900 G5.

Select whether to enable KTI prefetch. KTI prefetch enables memory read operations on DDR bus to be carried out earlier.

Options:

·     Auto.

·     Enabled.

·     Disabled.

Auto

SNC(Sub NUMA)

Select whether to enable sub NUMA clustering (SNC). SNC can shorten the delay between the LLC and the memory.

For the servers except for the B5700, R4300, R4700, R4900, R5300, and R5500 G5, options:

·     Enabled.

·     Disabled.

For the B5700, R4300, R4700, R4900, R5300, and R5500 G5, options:

·     Enable SNC2 (2-clusters)—To enable SNC, make sure the value of the MMCFG Base is an integer, for example, 1, 2, or 3 G.

·     Disabled.

Disabled

XPT Prefetch

Select whether to enable XPT prefetch.

Options:

·     Auto.

·     Enabled.

·     Disabled.

Auto

Stale AtoS

Select whether to enable the change from state A to S.

There are three states of cache directory: I stands for invalid; A stands for snooping all; S stands for shared. State AtoS enables the other rows to enter S state when the system reads from a row in A state and the other rows respond no match. This shortens latency of repeated cache reading without affecting writing and saves bandwidth. As a best practice, enable this feature if there are a lot of reading tasks across the sockets.

Options:

·     Auto.

·     Enabled.

·     Disabled.

Auto

LLC dead line alloc

Select whether to enable LLC dead line allocation. In the processor cache scheme, mid-level cache (MLC) evictions are filled into the last level cache (LLC). If a line is evicted from the MLC to the LLC, the processor can flag the evicted MLC lines as "dead." This means that the lines are not likely to be read again. This option allows dead lines to be dropped and never fill the LLC if the option is disabled.

Options:

·     Auto.

·     Enabled—Fills free LLC space with dead rows.

·     Disabled—Discards dead rows to save LLC space.

Enabled

Number of CPU

Displays the number of CPUs.

Number of IIO

Displays the number of IIOs.

Current UPI Link Speed

Displays the link speed of the current UPI.

Current UPI Link Frequency

Displays the link frequency of the current UPI.

Global MMIO Low Base / Limit

Displays the low base/limit of the global MMIO.

Global MMIO High Base / Limit

Displays the high base/limit of the global MMIO.

Pci-e Configuration Base / Size

Displays the base/size of the UPI PCIe configuration.

Enforce POR

Select whether to enforce POR restrictions on DDR4 frequency selection to improve memory reliability.

Options:

·     Enforce POR.

·     Disabled.

As a best practice, do not disable this feature.

Enforce POR

Enforce Population POR

Specify how to enforce memory population rule.

Options:

·     Disable Enforcement.

·     Enforce Supported Populations—Fills supported memory, including validated memory and non-validated memory.

·     Enforce Validated Populations—Only fills validated memory.

Enforce Supported Populations

Memory Frequency

Select the maximum memory frequency, in MHz.

Options:

·     Auto.

·     2400.

·     2666.

·     2933.

·     3200.

Auto

Attempt Fast Boot

Select whether to enable fast boot attempt.

Options:

·     Enabled—Enables fast boot. If skipping part of memory reference code (MRC) can speed up the warm boot process, the system skips this part of MRC.

·     Disabled—Disables fast boot.

Enabled

Attempt Fast Cold Boot

Select whether to enable fast cold boot attempt.

Options:

·     Enabled—Enables fast cold boot. If skipping part of MRC can speed up the cold boot process, the system skips this part of MRC.

·     Disabled—Disables fast cold boot.

Enabled

RMT On Cold Fast Boot

Select whether to enable rank margin tool (RMT) during cold fast boot.

Options:

·     Enabled.

·     Disabled.

Disabled

Rank Margin Tool

Select whether to turn on the Rank Margin Tool to test memory timing and voltage signals.

Options:

·     Enabled—Runs the Rank Margin Tool after memory training.

·     Disabled—Disables the Rank Margin Tool.

Disabled

Enable ADR

Select whether to enable asynchronous DIMM self-refresh (ADR) check.

Options:

·     Enabled.

·     Disabled.

Enabled

2x Refresh Enable

Select whether to enable two times of memory refresh.

Options:

·     Auto.

·     Enabled.

·     Disabled.

Auto

Memory Topology

Access the submenu that displays memory information, as shown in Figure 62.

The submenu items are described in Table 17.

N/A

Memory Map

Access the submenu for configuring memory mapping and interleaving, as shown in.

You can enable memory interleaving to improve memory read and write performance.

The submenu items are described in Table 18.

N/A

Memory RAS Configuration

Access the submenu for configuring memory reliability, availability, and serviceability (RAS) settings, as shown in Figure 65 and Figure 66.

The submenu items are described in Table 20.

N/A

PMem Configuration

This item is available only when Barlow Pass (BPS) memory modules are present.

Access the submenu for configuring persistent memory (PMem).

N/A

DIMM Status: Enabled CPU1_CH1_D0: 3200MT/s Micron DRx4 32GB RDIMM

Display the DIMM status, location, and other information. For example, DIMM Status: Enabled CPU1_CH1_D0: 3200MT/s Micron DRx4 32GB RDIMM, where:

·     DIMM Status: Enabled—DIMM status, which is enabled.

·     CPU1_CH1_D0—DIMM location, which is DIMM slot 0 of channel 1 for CPU1.

·     3200MT/s—DIMM frequency.

·     Micron—DIMM vendor.

·     DRx4—DR stands for the number of ranks. x4 indicates the bit width of a DIMM chip.

·     32GB—Capacity of the DIMM.

·     RDIMM—Type of the DIMM.

Volatile Memory Mode

Set the volatile memory mode for PMem.

Options:

·     2LM—Sets the 2 Level Memory (2LM) mode. In this mode, 2LM facilitates DDR4 memory as cache and PMem can operate in volatile memory mode. To configure Memory Mode (MM) for PMem, you must also configure settings on the PMem configuration subscreen.

·     1LM—Sets the 1 Level Memory (1LM) mode. In this mode, DDR4 memory acts as ordinary memory and PMem can operate in App Direct (AD) mode.

1LM

AppDirect cache

Select Enabled or Disabled to enable or disable caching for the memory region.

This item is available only when the volatile memory mode is 2LM.

Disabled

eADR Support

Select whether to enable the eADR capability in the platform.

Options:

·     Enabled.

·     Disabled.

·     Auto.

Do not enable eADR and ADR at the same time.

Disabled

CPU Cache Flush Mode

Select the processor cache flush execution mode.

Options:

·     Parallel.

·     Serial.

Parallel

Item

Description

Default

New SDDC Mode

This item is not available for the R6900 G5.

Select Enabled or Disabled to enable or disable SDDC mode.

Enabled

Mirror Mode

This item is unconfigurable when UEFI ARM Mirror or ADDDC Sparing is set to Enabled.

Specify a mirror mode.

Options:

·     Disabled—Disables mirror mode.

·     Full Mirror Mode—Sets all 1LM memory to operate in mirror mode, which reduces the available memory capacity by half.

·     Partial Mirror Mode—Enables partial mirror mode. In this mode, you can set the memory size of the mirror.

·     Due to hardware limitations, a segment of address space must be equally divided among the socket, IMC, Channel and rank. Therefore, when all the DIMMs are present, the memory capacity displayed in the POST screen and BIOS Setup utility is greater than half of the total memory capacity in the full mirror mode.

·     Enabling any type of mirror mode will disable XPT prefetch.

Disabled

Partial Mirror x Size(GB)

This item is available only when the Mirror Mode is set to Partial Mirror Mode.

Set the size of the partial mirror.

N/A

Mirror TAD0

This item is unconfigurable when Mirror Mode is set to Full Mirror Mode or ADDDC Sparing is set to Enabled.

Select Enabled or Disabled to enable or disable the mirror target address decoder (TAD0) mode.

If Enabled is selected, the memory saved for MMIO will be used for mirroring.

Disabled

UEFI ARM Mirror

This item is unconfigurable when Mirrorr Mode is not disabled or ADDDC Sparing is set to Enabled.

Select Enabled or Disabled to enable or disable UEFI ARM mirror mode.

Disabled

ARM Mirror percentage

Set the ARM mirror percentage. For example, 12.75% can be written as 1275.

N/A

Correctable Error Threshold

Set the correctable error threshold in decimal notation.

Value range: 0 to 32767.

Value 0 indicates that no correctable error threshold is set.

8192

Leaky bucket low bit

This item is configurable only when Memory Rank Sparing is set to Enabled.

Set the leaky bucket low bit in the range of 0 to 0x3F in hexadecimal notation.

0x10

Leaky bucket high bit

This item is configurable only when Memory Rank Sparing is set to Enabled.

Set the leaky bucket high bit in the range of 0 to 0x29 in hexadecimal notation.

0x11

ADDDC Sparing

This item is unconfigurable when Mirror Mode is set to Partial Mirror Mode or Full Mirror Mode.

Select Enabled or Disabled to enable or disable adaptive double device data correction (ADDDC) sparing.